Synthesis of Electronic Systems 1
6 ECTS
(3 hours classes, 2 hours labs)
Content: Simulation of analogue circuits using the PSPICE software. Active filters. Phase-locked loops, utilization in frequency synthesizers and in data transmission. The VHDL language and its use in the design and simulation of combinatorial and sequential circuits. Implementation by PLD. System design with emphasis on maximum speed - pipelining, parallelism.